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Features
* * * * * * *
Pulse-width Modulation up to 2 kHz Clock Frequency Protection Against Short-circuit, Load Dump Overvoltage and Reverse VS Duty Cycle 18 to 100% Continuously Internally Reduced Pulse Slope of Lamp's Voltage Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1 Charge-pump Noise Suppression Ground-wire Breakage Protection
Description
The U6083B is a PWM IC in bipolar technology for the control of an N-channel power MOSFET used as a high-side switch. The IC is ideal for use in brightness control systems (dimming) of lamps, for example, in dashboard applications.
PWM Power Control IC with Interference Suppression U6083B
Rev. 4770A-AUTO-11/03
Figure 1. Block Diagram with External Circuit
VS 1 5
C5 Rsh 6
VBatt
Current monitoring + short circuit detection
C1
4
RC oscillator PWM Logic Control input
Charge pump
7 C3 47 nF 8
47 k
3 Duty cycle reduction GND 2
Output
C2
Duty cycle range 18 to 100%
Voltage monitoring
Slew rate control
150
R3 Ground
2
U6083B
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U6083B
Pin Configuration
Figure 2. Pinning DIP8
1 2 3 4 OUTPUT 2 VS SENSE DELAY
VS GND VI OSC
8 7 6 5
Pin Description
Pin 1 2 3 4 5 6 7 8 Symbol VS GND VI OSC DELAY SENSE 2 VS OUTPUT Function Supply voltage VS IC ground Control input (duty cycle) Oscillator Short-circuit protection delay Current sensing Voltage doubler Output
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Functional Description
Pin 1, Supply Voltage, VS or VBatt
Overvoltage Detection Stage 1 If overvoltages of VBatt > 20 V (typically) occur, the external transistor is switched off, and switched on again at VBatt < 18.5 V (hysteresis). If VBatt > 28.5 V (typically), the voltage limitation of the IC is reduced from VS = 26 V to 20 V. The gate of the external transistor remains at the potential of the IC ground, thus producing voltage sharing between FET and lamps in the event of overvoltage pulses (e.g., load dump). The short-circuit protection is not in operation. At VBatt approximately < 23 V, the overvoltage detection stage 2 is switched off. Thus, during overvoltage detection stage 2, the lamp voltage Vlamp is calculated as follows: VLamp = VBatt - VS - VGS VS = supply voltage of the IC at overvoltage detection stage 2 VGS = gate - source voltage of the FET Undervoltage Detection In the event of voltages of approximately VBatt < 5.0 V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt 5.4 V.
Stage 2
Pin 2, GND
Ground-wire Breakage To protect the FET in the case of ground-wire breakage, a 1 MW resistor between gate and source is recommended to provide proper switch-off conditions. The pulse width is controlled by means of an external potentiometer (47 kW). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied from 18 to 100%. It is possible to further restrict the duty cycle with the resistors R1 and R2 (see Figure 4 on page 10). In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC automatically reduces the maximum duty cycle at pin 8 if the supply voltage exceeds V 2 = 13 V. Pin 3 is protected against short-circuit to V Batt and ground (VBatt 16.5 V).
Pin 3, Control Input
Pin 4, Oscillator
The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double current, 2 I, from the charging current. The capacitor, C 2 , is thus discharged at the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more.
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Example for Oscillator Frequency Calculation Switching thresholds VT100 VT100 VT<100 VT<100 VTL VTL where = High switching threshold (100% duty cycle) = VS a1 = (VBatt - IS R3) a1 = High switching threshold (< 100% duty cycle) = VS a2 = (VBatt - IS R3) a2 = Low switching threshold = VS a3 = (VBatt - IS R3) a3
a1, a2 and a3 are fixed values
Calculation Example The above mentioned threshold voltages are calculated for the following values given in the data sheet. VBatt VT100 VT<100 VTL Oscillator Frequency = 12 V, IS = 4 mA, R3 = 150 W, a1 = 0.7, a2 = 0.67 and a3 = 0.28 = (12 V - 4 mA 150 W) 0.7 8 V = 11.4 V 0.67 = 7.6 V = 11.4 V 0.28 = 3.2 V
3 cases have to be distinguished 1. f1 for duty cycle = 100%, no slope reduction with capacitor C4 (see Figure 4 on page 10)
I OSC f 1 = --------------------------------------------------------- , where C2 = 68 nF, IOSC = 45 A 2 ( V T100 - V TL ) C2
f1 = ... = 75 Hz 2. f2 for duty cycle < 100%, no slope reduction with capacitor C4 For a duty cycle of less than 100%, the oscillator frequency, f, is as follows:
I OSC f 2 = ------------------------------------------------------------ , where C2 = 68 nF, IOSC = 45 A 2 ( V T<100 - V TL ) C2
f2 = ... = 69 Hz 3. f3 with duty cycle < 100% with slope reduction capacitor C4 (see "Output Slope Control" on page 6)
Iosc f 3 = -----------------------------------------------------------------------------------------------2 ( V T<100 - V TL ) C2 + 2VBatt C 4
where C2 = 68 nF, IOSC = 45 A, C4 = 1.8 nF f3 = ... = 70 Hz By selecting different values of C2 and C4, it is possible to have a range of oscillator frequencies from 10 to 2000 Hz as shown in the data sheet.
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Output Slope Control
The slope of the lamp voltage is internally limited to reduce radio interference by limitation of the voltage gain of the PWM comparator. Thus, the voltage rise on the lamp is proportional to the oscillator voltage increase at the switchover time according to the equation. dV8/dt = a4 dV4/dt = 2 a4 f (a2 - a3) (VBatt - IS R3) when f = 75 Hz, VTX = VT < 100 and a4 = 63 then dV8/dt = 2 63 75 Hz (0.67 - 0.28) (12 V - 4 mA 15 W) = 42 V/ms Via an external capacitor, C4, the slope can be further reduced as follows: dV8/dt = IOSC/(C4 + C2/a4) when IOSC = 45 A, C4 = 1.8 nF, C2 = 68 nF and a4 = 63 then dV8/dt = 45 A/(1.8 nF + 68 nF/63) = 15.6 V/ms To damp oscillation tendencies, a resistance of 100 W in series with capacitance C4 is recommended.
Interference Suppression
* * * * * * *
"On-board" radio reception according to VDE 0879 part 3/4.81 Test conditions refering to Figure 3 Application circuit according to Figure 1 on page 2 or Figure 4 on page 10 Load: nine 4 W lamps in parallel Duty cycle = 18% VBatt = 12 V fOsc = 100 Hz
Figure 3. Voltage Spectrum of On-board Radio Reception
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U6083B
Pins 5 and Pin 6, Short-circuit Protection and Current Sensing
Short-circuit Detection and Time Delay, td The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the threshold for the short-circuit detection circuit (VT2 90 mV), the duty cycle is switched over to 100% and the capacitor C5 is charged by a current source of Ich - Idis. The external FET again is switched off after the cut-off threshold (VT5 ) is reached. Switching on the FET again is possible after a power-on reset only. The current source, Idis, ensures that the capacitor C5 is not charged by parasitic currents. The time delay, td, is calculated as follows: td = C5 VT5/(Ich - Idis) With C5 = 100 nF and VT5 = 10.4 V, Ich =13 A, Idis = 3 A, the time delay is as follows: td = 100 nF 10.4 V/(13 A - 3 A) td = 104 ms Current Limitation The lamp current is limited by a control amplifier to protect the external power transistor. The voltage drop across the external shunt resistor acts as the measured variable. Current limitation takes place for a voltage drop of VT1 100 mV. Owing to the difference VT1 - VT2 10 mV, it ensures that current limitation occurs only when the short-circuit detection circuit has responded. After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time.
Pins 7 and 8, Charge Pump and Output
Pin 8 (output) is suitable for controlling a power MOSFET. During the active integration phase, the supply current of the operational amplifier is mainly supplied by the capacitor C3 (bootstrapping). In addition, a trickle charge is generated by an integrated oscillator (f7 400 kHz) and a voltage doubler circuit. This permits a gate voltage supply at a duty cycle of 100%.
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Junction temperature Ambient temperature range Storage temperature range Symbol Tj Tamb Tstg Value 150 -40 to +110 -55 to +125 Unit C C C
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 120 Unit K/W
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Electrical Characteristics
Tamb = -40C to +110C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 2). All other values refer to pin GND (pin 2).
Parameters Current consumption Supply voltage Stabilized voltage Battery undervoltage detection Battery Overvoltage Detection Stage 1: Stage 2: Detection stage 2 Stabilized voltage Short-circuit Protection Short-circuit current limitation Short-circuit detection VT1 = VS - V6 VT2 = VS - V6 VT2 = VS - V6 5 VT5 Ich Idis I5 = Ich - Idis 7 Duty cycle 100% V7 f7 I7 = 5 mA (whichever is lower) dv8/dt = a4 dV4/dt dV8/dtmax 8 Low level Voltage VBatt = 16.5 V Tamb = 110C, R3 = 150 W High level, duty cycle 100% Current V8 = Low level V8 = High level, I7 > 1/2 I8 1/2 Min: C2 = 68 nF Max: VBatt 12.4 V VBatt = 16.5 V, C2 = 68 nF V8 V8 V8 I8 I8 tp/T 1.0 -1.0 15 100 65 18 73 21 % 81 V7 0.35 0.70 0.95 1.5(1) V V V mA mA V7 V7 a4 2 VS 280 26 VS+14 53 400 27.5 VS+15 63 520 30.0 VS+16 72 130 kHz V V V/ms I5 5 10.2 10.4 13 3 10 15 10.6 V A A mA VT5 = VS - V5 on off on off IS = 30 mA 1 6 VT1 VT2 VT1 - VT2 85 75 3 100 90 10 120 105 30 mV mV mV VBatt VBatt Vs 18.3 16.7 25.5 19.5 18.5 20.0 18.5 28.5 23.0 20.0 21.7 20.3 32.5 26.5 21.5 V V V V V Overvoltage detection, stage 1 IS = 10 mA on off 1 Test Conditions Pin 1 Symbol IS VBatt Vs VBatt 24.5 4.4 4.8 5.0 5.4 Min. Typ. Max. 7.9 25 27.0 5.6 6.0 Unit mA V V V
Delay Timer Short-ciruit Detection, VBatt = 12 V Switched off threshold Charge current Discharge current Capacitance current Voltage Doubler Voltage Oscillator frequency Internal voltage limitation Edge steepness Gate Output
Duty cycle Note:
1. Reference point is battery ground
8
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U6083B
Electrical Characteristics (Continued)
Tamb = -40C to +110C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 2). All other values refer to pin GND (pin 2).
Parameters Oscillator Frequency Threshold cycle V T100 V 8 = High, a 1 = -------------VS VT<100 V 8 = Low, a 2 = ---------------VS V TL a 3 = -------VS VBatt = 12 V C4 open, C2 = 68 nF duty cycle = 50% 4 f a1 10 0.68 0.7 2000 0.72 Hz Test Conditions Pin Symbol Min. Typ. Max. Unit
Upper
a2
0.65
0.67
0.69
Lower Oscillator current Frequency Note:
a3 IOSC f
0.26 34 56
0.28 45 75
0.3 54 90 A Hz
1. Reference point is battery ground
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Application
Figure 4. Application Circuit
10
C5 VS VS VS + + Current limiting 10 mV + 6 Idis + Reset Switch-on delay 63 x R R C3 Overvoltage monitoring stage 2 8 Reset 1 M 47 nF 7 Reset Voltage doubler VS C4 1.8 nF Ich 90 mV Rsh VS 5 VS 1 100 nF VBatt GND 2 150 R3 Ground Load RL
U6083B
VS
R1
I
4
Oscillator
C1
47 F
C2
68 nF
2I
VS
47 k 3
R2
VS
Overvoltage monitoring stage 1
VS
Low voltage monitoring
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U6083B
Ordering Information
Extended Type Number U6083B Package DIP8 Remarks -
Package Information
Package DIP8
Dimensions in mm
9.8 9.5 1.64 1.44 7.77 7.47
4.8 max 6.4 max 0.5 min 3.3 0.58 0.48 7.62 8 5 2.54 0.36 max 9.8 8.2
technical drawings according to DIN specifications
1
4
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4770A-AUTO-11/03
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4770A-AUTO-11/03

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